Proposal

To emulate the ET-3400 Heathkit using a microcoded version of the Motorola M6800 Central Processing Unit.

M6800 Information

The M6800 is a monolithic 8-bit microprocessor forming the central control function for Motorola’s M6800 family.  It is capable of addressing 64K bytes of memory with its 16 address lines.  The 8-bit data bus is bi-directional allowing direct memory access and multiprocessing applications possible.

Properties: 

• 8-bit Data Bus
• 16-bit Address Bus
• Variable Length Stack
• Vectored Restart
• Clock Rate of up to 2.0Mhz
• Six Internal Registers
• Accumulator A and B
• Index Register
• Program Counter
• Stack Pointer
• Condition Code Register
• Seven addressing modes:
• Direct
• Relative
• Immediate
• Indexed
• Extended
• Implied
• Accumulator

Tasks

Loading Micro-Vector/Control Store Rom/ROM images from disk.

These three images will be stored locally in a .ROM file, and will be read in using existing C++ input streams.  The Control Store Rom will be loading separately into its own array, as with the Micro-vector array.  The ROM on the other hand will be loaded into the appropriate location in the simulated main memory, which is located at FC00 to FFFF.  It will be known that main memory will consist of an array of 64Kb and the Micro-Vector will be implemented as an array of size 256.  It is unknown at this time how large the Control Store Rom will be, and will depend on the amount of microcode that will have to be written.

The micro instruction sequencer code

This will be the heart of the emulation software, and will consist of a switch statement that represents the multiplexer.  This main body will run in a continuous loop and will look very similar to below:

In order to simulate the various registers and buffers, there will be the appropriate memory reserved for each.  An 8-bit register or buffer will be declared as an unsigned char, while a 16-bit register or buffer will be an unsigned short int.  A list of the registers and buffers can be found in the Internal Structure diagram.

Implementation of micro-instruction set

Each macro instruction will require a series of micro instructions to implement it. As with the opcodes given to the macro instructions, a set of micro-opcodes will be given to each possible micro instruction.  These opcodes will be arranged bit-wise and will allow easy decoding.  A number of opcodes have been reserved for future use, in the case of any unforeseen difficulty.  Currently the opcode list consists of the following:

 

ENABLE CLOCK -1      0      -- +1      1      -- ALU1    -      34 ALU2    -      35 ALURES  4      -- MAR     5      37 MBR     6      38 PCHI    7      39 PCLO    8      40 SP      9      41 ACCA    10     42 ACCB    11     43 PC      12     44 IR      13     45 X       14     46 XLO     15     47 XHI     16     48 SPLO    17     49 SPHI    18     50 CCR     19     51 0       20     -- TLO     21     53 THI     22     54 T       23     55 ALU1HI  --     56 ALU1LO  --     57 ALU2HI  --     58 ALU2LO  --     59 ALURESHI28     -- ALURESLO29     --   MEMRD   64 MEMWR   96     ALUCON (100xxxxx) ADD     128    Addition SUB     129    Subtract AND     130    AND IOR     131    Incl. OR EOR     132    Excl. OR NOT     133    NOT SGN     134    SGN ADD ROL     135    R Left ROR     136    R Right SLA     137    S Left A SRA     138    S Right A SRL     139    S Right L ADC     140    Add Carry SBC     141    Sub Carry DAA     142    D Adjust

FCC     160 (101 xxxxx) FCS     161 FEQ     162 FGE     163 FGT     164 FHI     165 FLE     166 FLS     167 FLT     168 FMI     169 FNE     170 FVC     171 FVS     172 FPL     173 FSR     174 CLRH    192 (110 xx xxx) CLRI    193 CLRN    194 CLRZ    195 00 = clr   000 = h CLRV    196 01 = set   001 = i CLRC    197 10 = clk   010 = n SETH    200            011 = z SETI    201            100 = v SETN    202            101 = c SETZ    203 SETV    204 11 = spec SETC    205 CLKH    208 CLKI    209 CLKN    210 CLKZ    211 CLKV    212 CLKC    213 SP1     217 SP2     218 SP4     220 SP5     221 SP6     222 SP7     223 SP8     224   EXECUTE 254 FETCH   255

This is only a working model as it stands, and will be changed as time goes on. Also a more concrete standard will be set to put them in a more standard naming convention.

Micro Assembler

In order to make coding much simpler and easier to debug, a micro assembler will be written that will parse a file and create the Control Store .ROM file. In order to differentiate between macro instructions, several conventions must be made.  When starting to write new microcode sequences for particular macro instructions, a “VEC <MacroInstruction Name>” will be used to partition each.  Also in order to equate macro-opcodes with the written conventional name, there will be statements at the top that have the form “<MacroInstruction Name> EQU <Macroinstruction Opcode>”.  The keyword ORG will also be placed just prior to the start of the micro-routines to show where they start.  An example from the current set is shown below:

The FETCH and EXECUTE micro routines will have their locations loaded into the micro sequencer from a separate .reg file, so it will know exactly where they are located for quick access.

A Macros function will also be incorporated to reduce the final size of the microprogramming, and to allow modularization.  A macros will be defined between the two key words DEFMAC and ENDMAC, with the macros name being placed directly after the DEFMAC.  To use a macros in the microcoding, one would call it with it’s name after the keyword MACRO.  An example is shown below:

Seven Segment Display

Since the display outputs are memory-mapped, an appropriate co-routine will be written to be monitoring the memory locations and appropriately display the seven segment display.  This will be done graphically, and done in the conventional LED format of digits. The memory locations of C110 to C16F will contain the specific addresses in which each specific LED is defined.

Input Pad

The input pad behaves slightly differently than the displays, but still has memory locations associated with it (C003 to C00E).  When a key is pressed a crossbar connects the appropriate “row” with “column” and the appropriate signal is sent out through the data bus. A general scheme will be developed to allow input of all 17 inputs, and most likely will be by means of a graphical display in which the user clicks on each given key with the mouse.

Graphical Model

The graphical model will consist of two levels.  The first level will be the Heathkit emulation model which will run at the macro level.  This will consist of the keyboard display and the seven digit segment display.  The second level, which will most likely be launched by means of a toggle switch, will show every detail in the micro level. Careful preparation will have to be taken to only run this model only while a user program is running, and not the Heathkit software since the cycle time will have to be decreased dramatically while running in “micro” level in order to show the detail.  This detail will include signals on each line, as well as register and buffer values.  The micro-sequencer model given in Machine Structures will be used as a basis for the micro level.

Final Presentation

The final presentation will be given to the current Computer Science faculty, in which the working model will be shown, as well as a brief presentation on how it works.  Each faculty member will contribute 8% towards the final grade based on the presentation and final product.